On-time Network On-Chip: Analysis and Architecture

Authors:
Bui, Dai
Pinto, Alessandro
Lee, Edward A.
Technical Report Identifier: EECS-2009-59
May 8, 2009
EECS-2009-59.pdf

Abstract: Game, multimedia, consumer and control applications demand low power and high performance computing platforms capable of providing real-time services. Multi-core architectures, supported by on-chip networks, are emerging as scalable solutions to fulfill these requirements. However, the increasing number of concurrent applications running on these platforms, and the time-varying nature of their communications give rise to unpredictable delays.

We propose simple and flexible on-chip protocol and architecture that provide application level communication services with end-to-end timing guarantees. We prove the correctness of our protocol using analytical models and we validate our implementation using detailed simulations.