University of California, Berkeley
EECS Technical Reports
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Terms: 1993
Results: 171 item(s)
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Title:   Papyrus: A History-Based VLSI Design Process Management System 100
  Author(s):   Chiueh, Tzi-cker      
  Report ID:   CSD-93-724  

Title:   TIMING ISSUES IN SEQUENTIAL CIRCUITS 100
  Author(s):   Shenoy, Narendra Vasudeva      
  Report ID:   ERL-93-97  

Title:   A DEXTROUS MASTER FOR TELESURGERY 100
  Author(s):   Crawford, Lara S.      
  Report ID:   ERL-93-95  

Title:   AN EXACT LOGIC MINIMIZER USING IMPLICIT BINARY DECISION DIAGRAM BASED METHODS 100
  Author(s):   SWAMY, UITANJALI M.      
  Report ID:   ERL-93-94  

Title:   THE SIMPLEST DISSIPATIVE NON-AUTONOMOUS CHAOTIC CIRCUIT 100
  Author(s):   Murali, K. Lakshaman, M. Chua, L.O.      
  Report ID:   ERL-93-93  

Title:   TIME SCALE TO ERGODICITY IN THE FPU SYSTEM 100
  Author(s):   De Luca, J    Lichtenberg, A. J.    Lieberman, M. A.      
  Report ID:   ERL-93-92  

Title:   Concurrent Circuit Design/Process Engineering in a Flexible Manufacturing Environment 100
  Author(s):   Neureuther, Andy    Spanos, Costas J.    Hatzilambrou, Mark    Yu, Crid      
  Report ID:   ERL-93-91  

Title:   DORIC: DESIGN OF OPTIMIZED AND ROBUST INTEGRATED CIRCUITS 100
  Author(s):   Daoud, Zeina      
  Report ID:   ERL-93-90  

Title:   Nonholonomic Motion Planning for Underwater Vehicles 100
  Author(s):   Tennant, Jean-Paul      
  Report ID:   ERL-93-89  

Title:   The Learning Problem For Discrete-Time Cellular Neural Networks as a Combinatorial Optimization Problem 100
  Author(s):   Magnussen, Holger    Nossek, Josef A.    Chua, Leon 0.      
  Report ID:   ERL-93-88  

Title:   Hyperchaotic Attractors of UniDirectionally-Coupled Chua's Circuits 100
  Author(s):   Kapitaniak, Tomasz    Chua, Leon O.      
  Report ID:   ERL-93-87  

Title:   Simulations of Limiting Current in a Crossed-Field Gap: Hall Diode 100
  Author(s):   Verboncoeur, J. P.    Birdsall, C. K.      
  Report ID:   ERL-93-86  

Title:   Direct Aerial Image Measurements at 248nm 100
  Author(s):   Fields, Charles H.      
  Report ID:   ERL-93-85  

Title:   Computing Boolean Expressions With OBDDs 100
  Author(s):   Shiple, Thomas R.    Brayton, Robert K.    Sangiovanni-Vincentelli, Alberto L.      
  Report ID:   ERL-93-84  

Title:   Flexibility in the Interactions Between High-Speed Networks and Communications Applications 100
  Author(s):   Haskell, Paul Eric      
  Report ID:   ERL-93-83  

Title:   A Physical Poly-Silicon Thin Film Transistor (TFT) Model for Circuit Simulation 100
  Author(s):   Li, Chester      
  Report ID:   ERL-93-82  

Title:   COMBINED HIERARCHICAL APPROACHES TO INTEGRATED CIRCUIT LAYOUT BASEd ON A COMMON DATA MODEL 100
  Author(s):   Lee, Brian Douglas Ngai      
  Report ID:   ERL-93-81  

Title:   Novel Techniques for High Performance Field Programmable Logic Devices 100
  Author(s):   Bhat, Narasimha B.      
  Report ID:   ERL-93-80  

Title:   A Fully Implicit Algorithm for Exact State Minimization 100
  Author(s):   Kam, Timothy    Villa, Tiziano    Brayton, Robert K.    Sangiovanni-Vincentelli, Alberto      
  Report ID:   ERL-93-79  

Title:   Long Run Dynamics of Queues: Stability and Chaos 100
  Author(s):   Friedman, Eric J.    Landsberg, A. S.      
  Report ID:   ERL-93-78  

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