University of California, Berkeley
EECS Technical Reports
Search | Browse by year
Terms: 1993
Results: 171 item(s)
Sorted by: Relevance | Year Page: Prev  1 2 3 4 5   ...  Next
Relevance
Title:   A Method for Estimating Overlap Capacitance in Mosfet Devices by DC Current Measurement 100
  Author(s):   Bana, Soheila      
  Report ID:   ERL-93-77  

Title:   Short Run Dynamics of Multi-Class Queues 100
  Author(s):   Friedman, Eric J.    Landsberg, A. S.      
  Report ID:   ERL-93-76  

Title:   Integrating Price-Based Resources in Short-Term Scheduling of Electric Power Systems 100
  Author(s):   Svoboda, Alva J.    Oren, Shmuel S.      
  Report ID:   ERL-93-75  

Title:   Modeling Electronegative Plasma Discharges 100
  Author(s):   Lichtenberg, A. J.    Vahedi, V.    Lieberman, M. A.    Rognlien, T.      
  Report ID:   ERL-93-74  

Title:   A Simple Way to Synchronize Chaotic Systems with Applications to Secure Communication Systems 100
  Author(s):   Chua, Leon O.    Wu, Chai Wah      
  Report ID:   ERL-93-73  

Title:   Low-Power High-Speed DSP Architecture For Magnetic Disk PRML Read Channel 100
  Author(s):   Wong, See-Hoi Caesar      
  Report ID:   ERL-93-72  

Title:   BDD Variable Ordering for Interacting Finite State Machines 100
  Author(s):   Aziz, Adnan    Tasiran, Serdar    Brayton, Robert K.      
  Report ID:   ERL-93-71  

Title:   XPole: An Interactive, Graphical Signal Analysis Filter Design Tool 100
  Author(s):   White, Kennard      
  Report ID:   ERL-93-70  

Title:   Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model 100
  Author(s):   Buck, Joseph Tobin      
  Report ID:   ERL-93-69  

Title:   Minimizing Interacting Finite State 100
  Author(s):   Aziz, Adnan    Singhal, Vigyan    Swamy, Gitanjali M.    Brayton, Robert K.      
  Report ID:   ERL-93-68  

Title:   Optimum Partitioning of Analog and Digital Circuitry in Mixed-Signal Circuits for Signal Processing 100
  Author(s):   Nishimura, Ken A.      
  Report ID:   ERL-93-67  

Title:   Multiprocessor DSP Code Synthesis in Ptolemy 100
  Author(s):   Murthy, Praveen Kumar      
  Report ID:   ERL-93-66  

Title:   Analysis of the Infopad Downlink 100
  Author(s):   Camagna, John      
  Report ID:   ERL-93-65  

Title:   Input Don't Care Sequences 100
  Author(s):   Wang, Huey-Yih    Brayton, Robert K.      
  Report ID:   ERL-93-64  

Title:   Multi-Bit [sigma-delta] Analog-to-Digital Converters with Nonlinearity Correction Using Dynamic Barrel Shifting 100
  Author(s):   Sakina, Yasuaki      
  Report ID:   ERL-93-63  

Title:   A Parallel Architecture for High-Data-Rate Digital Receivers in Scaled CMOS Technology 100
  Author(s):   Hu, Timothy Hak-Ting      
  Report ID:   ERL-93-62  

Title:   The Maximum Set of Permissible Behaviors for FSM Networks 100
  Author(s):   Watanabe, Yosinori    Brayton, Robert K.      
  Report ID:   ERL-93-61  

Title:   Implicit Generation of Compatibles for Exact State Minimization 100
  Author(s):   Kam, Timothy    Villa, Tiziano    Brayton, Robert K.    Sangiovanni-Vincentelli, Alberto      
  Report ID:   ERL-93-60  

Title:   A New Approach for the Synthesis of FSM's From Control-flow Graphs 100
  Author(s):   Sekine, Masatoshi    Villa, Tiziano    Goto, Kenji    Brayton, Robert K.      
  Report ID:   ERL-93-59  

Title:   Heuristic Minimization of BDDs Using Don't Cares 100
  Author(s):   Shiple, Thomas R.    Hojati, Ramin    Sangiovanni-Vincentelli, Alberto L.    Brayton, Robert K.      
  Report ID:   ERL-93-58  

Copyright © 2007 The Regents of the University of California. All rights reserved.